PCIE Design Validation Engineer
Core
Design validation for high-speed protocol IP cores (including PCIe) on Altera FPGA devices, ensuring robust functionality from simulation to hardware.
Role type
IC design validation engineer (FPGA IP)
Builds
High-speed protocol IP cores (interconnect, Ethernet, wireless) for Altera FPGA product portfolios
Domain
Semiconductor / FPGA / High-speed digital protocols
Deliverable
production ML models | product features | infrastructure
Required skills
FPGA prototyping, emulation, simulation, UVM, System Verilog, constrained random verification, assertion-based verification, functional coverage, RTL design (Verilog/VHDL), PCIe protocol knowledge
Preferred skills
Python, Perl, TCL, shell scripting, Quartus, Vivado, embedded SW/HW design, team leadership
Technologies
Quartus, Vivado, System Verilog, UVM, OVM, VMM
Responsibilities
Create comprehensive verification and validation plans; Develop IP/subsystem testbenches and coverage goals; Analyze results and debug failures; Support IP bring-up on FPGA development kits; Build FPGA emulation prototypes and validation frameworks; Develop verification tools and flows
Seniority
Mid-level IC engineer
