Senior Layout Engineer (M/F/D)
Core
Developing full-custom physical layouts for high-speed analog and mixed-signal integrated circuits (SiGe BiCMOS and CMOS) used in optical transceiver solutions.
Role type
Senior IC Layout Engineer
Builds
Optical transceiver building blocks (transmit, receive, bias, clocking circuits) for data center, telecom, and cloud infrastructure
Domain
Semiconductor / Optical Networking / IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full-custom layout in SiGe BiCMOS and CMOS, High-speed analog/mixed-signal design, Physical verification (DRC, LVS, ERC, parasitic extraction), Floorplanning and block integration, CAD and physical verification tools, Matching and symmetry optimization, Parasitic management
Preferred skills
Experience in optical transceiver applications, Knowledge of shielding and reliability considerations
Technologies
SiGe BiCMOS, CMOS, DRC, LVS, ERC, Parasitic extraction tools
Responsibilities
Develop full-custom layout for high-speed analog and mixed-signal IC blocks, Support implementation of layouts for optical transceiver building blocks, Work with circuit designers to optimize layout for performance and manufacturability, Perform physical verification including DRC, LVS, ERC, and parasitic extraction, Contribute to floorplanning and layout quality improvement, Apply engineering judgment to ensure robust layout solutions
Seniority
Senior, hands-on IC