Sr Layout Engineer
Core
Block level analog circuit design, simulation, schematic capture, layout verification, post-layout extraction, and top-level integration for integrated power semiconductors.
Role type
Senior IC analog layout engineer
Builds
Integrated power semiconductor chips and systems
Domain
Semiconductor / Analog IC design
Deliverable
production ML models | product features
Required skills
ADC design (SAR/Delta-Sigma/Counting/Pipelined), analog integrated circuit implementation, layout design and extraction, substrate coupling, LatchUp and ESD rules, transistor level analog and digital circuit theory, Cadence/Mentor tools proficiency
Preferred skills
Low-Noise Amplifier/Op-amp/RF design, digital design flow, analog/digital interface and integration, mixed-mode system level simulation (AMS) on SOC
Technologies
Cadence, Mentor
Responsibilities
Perform block level analog circuit design and simulation; execute schematic capture; conduct layout verification and post-layout extraction; manage top-level integration and verification
Seniority
Senior, hands-on IC
