Engineer 1
Core
Verifying complex CPU pipelines and memory subsystems, specifically ensuring architectural and microarchitectural correctness of the Memory Management Unit (MMU).
Role type
Hardware Verification Engineer (DV)
Builds
CPU cores and memory subsystems for RISC-V architecture
Domain
Semiconductor / Chip Design / Computer Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, Python, Perl, Bash, CPU core architecture, virtual memory, paging mechanisms, functional coverage analysis
Preferred skills
RISC-V ISA, assembly-level programming, C/C++ in embedded environments
Responsibilities
Participate in block-level and subsystem-level verification of the MMU including TLBs and page table walkers; Write, execute, and debug directed and random test cases; Analyze functional and code coverage metrics to identify verification gaps; Work closely with design and architecture teams to validate fixes.
Seniority
Entry-level (1+ years experience)
