Design Verification Engineer to Staff Engineer (Unit Level Test)
Core
Generate automated constrained random test cases and establish scalable, reusable test benches for CPU and memory subsystem designs.
Role type
Design Verification Engineer (Unit Level Test)
Builds
CPU cores, memory subsystems, and interconnects for RISC-V processors
Domain
Semiconductor / Chip Design / RISC-V Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Verilog, C++, C, Makefiles, scripting languages, AMBA protocols, processor/SoC architecture, functional coverage analysis, test plan generation, failure analysis
Preferred skills
AMBA protocol familiarity, memory subsystem expertise
Technologies
SystemVerilog, UVM, Verdi/DVE, Verilog, Makefiles
Responsibilities
Review and influence product definitions and specifications from a verification perspective; Develop checkers and assertions for memory subsystems and interconnects; Develop tools, test benches, and test suites; Develop and maintain in-house Verification IP (VIP); Write and analyze functional coverage to close coverage holes
Seniority
Mid-Senior (3+ years experience)
