Senior Lead Engineer - SoC Design Verification
Core
Design Verification Engineer executing complex SoC verification for ARM-based microcontrollers, focusing on low-power design, security IPs, and multiple interface verification.
Role type
Senior IC SoC Design Verification Engineer
Builds
Production SoCs and IP blocks for embedded microcontroller products
Domain
Semiconductor / Embedded Systems / SoC Design
Deliverable
production ML models | product features
Required skills
SoC-level verification, IP-level verification, UVM, SystemVerilog, Verilog, constrained-random verification, C-based DV, SVA, functional coverage, regression testing, RTL simulation, gate-level simulation, FPGA emulation, low-power verification (UPF), EDA tools (Synopsys VCS, Cadence Xcelium)
Preferred skills
Power-aware simulation, Flash memory verification, security IP verification, Analog IP verification (ADC, DAC, PLLs), interface verification (SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI)
Responsibilities
Develop and own SoC-level and IP-level verification suites with coverage goals; Execute verification plans per product specifications; Develop, debug, and run UVM-based verification environments; Define and develop test cases, stimulus, and assertions; Drive DV closure on diverse IPs and subsystems; Collaborate on verification flow improvements; Mentor junior team members
Seniority
Senior, hands-on IC
