PRINCIPAL PHYSICAL VERIFICATION ENGINEER
Core
Own full-chip and block-level physical verification (PV) signoff to ensure designs meet foundry and reliability requirements.
Role type
Principal Physical Verification Engineer (via careerplan.io/jobs/R-10064795-principal-physical-verification-engineer-at-nxp)
Builds
High-quality silicon tapeouts
Domain
Semiconductor / VLSI Design
Required skills
DRC, LVS, ERC, Antenna checks, Density checks, Reliability checks, Runset development, Flow automation, Hierarchical verification, Regression management, Foundry deck analysis, Tapeout readiness reviews, EM/IR analysis, Latch-up checks, ESD checks, Multi-patterning constraints, EUV constraints, PD-PV interaction analysis, SoC-level integration, Root cause correlation with PD
Preferred skills
Physical Design concepts (Floorplanning, PDN design), Placement/CTS/Routing flows, Flow automation methodology development
Technologies
EDA tools, PDKs, Foundry decks
Responsibilities
Perform DRC, LVS, ERC, and reliability checks; Drive signoff closure by resolving violations; Develop and maintain automation flows; Analyze foundry decks and PDK updates; Lead tapeout readiness reviews; Perform hierarchical verification and regression management; Interface with foundry and EDA vendors; Mentor junior engineers.
Seniority
Principal, hands-on IC with mentorship
