Stage ingénieur: Amélioration de la vérification d’un contrôleur I2C avec UVM, preuve formelle et IA (H/F)
Core
Improve verification coverage for an I2C module embedded in NFC components using formal verification and AI-driven testbench optimization.
Role type
Intern, Digital Verification Engineer (IP)
Builds
High-quality verification solutions for NFC components used in secure mobile transactions, payments, and IoT.
Domain
Semiconductor / Hardware Verification / NFC / Secure Transactions
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, Digital Design, Formal Verification, Testbench Development, Protocol Compliance Analysis
Preferred skills
AI/ML for test generation, Negative test scenario creation, Automated assertion generation
Technologies
UVM, SystemVerilog, I2C Protocol, AI/ML tools
Responsibilities
Review and take ownership of existing verification environment; Implement assertions and formal verification to justify waivers; Develop additional test scenarios to improve functional coverage; Investigate AI usage to generate negative test scenarios and auto-generate assertions; Check protocol compliance in specific I2C sequences.
Seniority
Intern (final year engineering student)
