Senior Analog Layout Engineer
Core
Designing high-quality analog mixed-signal IP layouts for PLLs, oscillators, data converters, and power management across advanced technology nodes.
Role type
Senior Analog Mixed-Signal Layout Engineer
Builds
High/low speed IOs, Clocking IP, Data Converter IPs, Power Management IPs
Domain
Semiconductor IC Design, Analog Mixed-Signal
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout techniques, EM/IR analysis, ESD reviews, Cadence Virtuoso, LEF/ndm/milkyway back-end view generation, layout matching, common centroid layout, IO pad ring design
Preferred skills
Experience with 5nm, 16ffc, 22fdx, 28nm, 40nm tech nodes
Technologies
Cadence Virtuoso, LEF, ndm, milkyway
Responsibilities
Collaborate with design teams to scope layout work for various IP blocks, interact with SoC teams to understand requirements, conduct ESD and layout reviews, perform EM/IR analysis, execute layout for sub-blocks to complex top-level IPs
Seniority
Senior, hands-on IC
