Senior CAD Engineer
Core
Build, enhance, and support scalable verification infrastructure, methodologies, and EDA automation flows for ASIC/SoC development to enable verification teams.
Role type
Senior IC CAD Engineer (Digital Verification)
Builds
Robust regression systems, automation frameworks, and advanced verification methodologies (UVM, coverage, CI/CD flows)
Domain
Semiconductor / ASIC/SoC Design / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
Digital verification flow expertise, System Verilog, UVM, Python/Tcl/Perl scripting, Linux environment management, EDA tool proficiency, regression/CI/CD system management, compute farm optimization
Preferred skills
AI/ML-based DV tools experience, cloud-based regression environments, CAD Application Engineer background
Technologies
VCS, Xcelium, Verdi, vManager, Cadence Verisium AI, LSF, Python, Tcl, Perl
Responsibilities
Act as primary support interface for DV teams on simulation, regression, and debug flows; Deploy, integrate, and maintain CAD tools and environments; Collaborate with DV teams to identify bottlenecks and provide solutions; Work with EDA vendors to track, debug, and escalate tool issues; Monitor and optimize infrastructure usage for efficient job execution; Provide methodology guidance and training to verification engineers
Seniority
Senior, hands-on IC
