Sr Synthesis and Implementation Engineer
Core
Translating RTL designs into optimized gate-level netlists for complex IP blocks while meeting performance, power, and area targets.
Role type
Senior IC synthesis and front-end implementation engineer
Builds
Digital ASIC/SoC IP blocks
Domain
Semiconductor hardware design (VLSI)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-gate synthesis, timing constraint development (SDC), static timing analysis (STA), formal verification (LEC), power analysis, area estimation, automation scripting (Tcl, Python, Perl), Verilog/SystemVerilog
Preferred skills
Physical synthesis, floorplanning, DFT principles, low-power design techniques
Technologies
Synopsys DC/FC, Cadence Genus, Synopsys PrimeTime, Cadence Tempus, Synopsys Formality, Cadence Conformal
Responsibilities
Perform logical and physical synthesis of RTL designs; develop timing constraints to achieve target frequencies; conduct STA and identify critical paths; execute formal verification to ensure functional equivalency; analyze and optimize power consumption; perform area estimation and optimization; collaborate with RTL, DFT, and physical design engineers; develop automation scripts for synthesis flows; evaluate and integrate new CAD tools; document design constraints and analysis results.
Seniority
Senior, hands-on IC