Principal Layout Engineer
Core
Lead a global team of analog layout engineers to design high-performance analog blocks and systems for microcontrollers, NFC, UWB, and Bluetooth products.
Role type
Principal Analog Layout Engineer (Team Lead)
Builds
High-performance analog and RF integrated circuits for MCUs and IoT edge solutions
Domain
Semiconductor / Analog IC Design / IoT
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout expertise, transistor-level IC fundamentals, layout matching and parasitics, DRC/LVS verification, LEF/Lib generation, automation scripting, cross-functional collaboration, team leadership
Preferred skills
Experience with multiple process nodes (140nm to 16nm), knowledge of ESD/Latch-up, signal chain and power design layouts
Technologies
Cadence Virtuoso, Siemens Calibre
Responsibilities
Lead a team of analog layout engineers, develop layout expertise and drive innovation, provide accurate estimates on area/performance/timeline, ensure layouts meet performance/power/area requirements, develop and maintain layout scripts and automation tools, perform layout verification and sign-off, deliver physical models to subsystem teams
Seniority
Principal, hands-on IC with team leadership