Senior Lead Engineer – Memory design
Core
Leading and managing a diverse Non-Volatile Memory (NVM) IP portfolio, developing automated IP management solutions, and collaborating with vendors and product teams to deliver scalable NVM IP solutions.
Role type
Senior Lead Engineer – Memory design (NVM IP)
Builds
NVM IP platform including Logic-NVM, Flash, RRAM, and MRAM for multiple business verticals
Domain
Semiconductor / Memory Design / IP Development
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog design, Memory design (SRAM/NVM), Foundation IP design (IO/standard cells), Scripting and flow automation, Cross-functional team leadership, Quality managed design flows, NVM technology knowledge, Macro architecture design
Preferred skills
NVM technology, macro architecture and design expertise
Technologies
Cadence, Synopsys, GDS
Responsibilities
Lead NVM IP benchmarking for product and technology requirements, Execute IP onboarding and release to product teams, Support product design teams with NVM IP integration and troubleshooting, Develop and maintain automated IP onboarding and release flows, Maintain 3rd-party and proprietary NVM IP portfolio from 180nm to 5nm, Interact with 3rd-party vendors and silicon foundries, Manage the complete NVM IP development lifecycle, Drive cross-functional coordination with digital design, reliability, and test engineering, Mentor junior engineers in NVM field
Seniority
Senior, hands-on IC with leadership responsibilities
