Principal HIG ESD and Latch-up Engineer- HBM - TPG
Core
Define and own chip-level and IP-level ESD and latch-up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces to ensure product reliability.
Role type
Principal HIG ESD and Latch-up Engineer (HBM)
Builds
Next-generation HBM solutions for AI and machine learning
Domain
Semiconductor memory (HBM/DRAM) and ESD physics
Deliverable
production ML models
Required skills
ESD physics fundamentals, latch-up mechanisms, advanced CMOS devices, ESD protection circuit design, latch-up prevention techniques, JEDEC/ESDA standards knowledge, silicon validation, failure analysis, foundry partnership management
Preferred skills
HBM/DRAM ESD sign-off experience, SCR-based clamp design, distributed ESD networks, rail-based strategies, foundry ESD team collaboration, engineering mentorship
Technologies
HBM, DRAM, TSV, JEDEC, ESDA, CDM, JESD78
Responsibilities
Define chip-level and IP-level ESD and latch-up strategies; Establish ESD and latch-up requirements and sign-off criteria; Enable ESD protection circuits and safe layout practices; Lead silicon validation and failure analysis; Act as technical interface to foundries
Seniority
Principal, hands-on IC with strategy & mentorship
