Principal HBM Design Architect
Core
Design, simulate, and optimize digital, analog, and mixed-signal DRAM circuits for next-generation High Bandwidth Memory (HBM) products supporting Machine Learning and AI applications.
Role type
Principal HBM Design Architect (Senior IC)
Builds
Highly reliable, industry-leading HBM solutions with TSV-based 3D integration and high-speed mixed-signal architectures.
Domain
Semiconductor / Memory / High-Speed Digital & Analog Design
Deliverable
production ML models
Required skills
CMOS circuit design, semiconductor device physics, schematic entry, circuit simulation (Finesim, HSPICE), power distribution analysis, scripting (Python, Tcl, Perl), timing optimization, floor planning, cross-domain integration.
Preferred skills
DRAM or memory design fundamentals, complex problem-solving, technical communication.
Technologies
Finesim, HSPICE, Python, Tcl, Perl, TSV, 3D integration.
Responsibilities
Design and analyze digital, analog, and mixed-signal circuits; perform schematic entry and simulation of DRAM blocks; evaluate full-chip functionality; conduct pathfinding and feasibility studies; optimize circuit timing, area, power, and complexity; support design floor planning and layout reviews; collaborate with global engineering teams; contribute to verification and validation strategies.
Seniority
Principal, hands-on IC with mentorship potential.
