RTL Design Engineer - MTS
Core
Designing and verifying on-chip memory controllers for NAND products, optimizing logic for performance, area, and power targets.
Role type
Senior RTL Design Engineer (Memory Controller)
Builds
On-chip memory controllers for NAND flash storage
Domain
Semiconductor / Memory Storage / Digital Logic Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design, Verilog, logic synthesis, verification planning, block-level design, system specification interpretation, architecture definition
Preferred skills
Mentorship, cross-functional collaboration, competitor analysis, training program development
Technologies
Verilog, RTL, synthesized netlist, gate level verification
Responsibilities
Own overall logic design of on-chip memory controller; Meet performance/area/power targets; Define and build design architecture spec documents; Perform RTL and synthesized netlist verification at block, subsystem, and fullchip level; Plan and prioritize projects and manage designers; Mentor new hires and supervise progress.
Seniority
Senior, hands-on IC with team leadership
