Senior Memory Circuit Design Verification Engineer (E3)
Core
Execute FastSpice-based verification and full-chip analog SPICE simulations for DRAM and HBM critical timing sign-off.
Role type
Senior IC memory circuit design verification engineer
Builds
DRAM and HBM memory products
Domain
Semiconductor memory (DRAM, HBM, SRAM)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
FastSpice tools (PrimeSim, FineSim, SpectreFx), analog and mixed-signal circuit analysis, DRAM memory architecture knowledge, SystemVerilog/UVM, Virtuoso, Xcelium, SimVision, WaveView, Python/Perl scripting
Preferred skills
DRAM/HBM/SRAM product experience, MS/M.Tech in Electrical/Electronics Engineering
Technologies
PrimeSim, FineSim, SpectreFx, HSPICE, Virtuoso, Xcelium, SimVision, WaveView, Python, Perl
Responsibilities
Execute FastSpice-based verification for DRAM and HBM critical timing sign-off; Perform full-chip and block-level analog SPICE simulations across PVT corners; Simulate, analyze, and debug pre-silicon designs to resolve functional and timing issues; Develop and maintain SPICE and mixed-signal testbenches; Create test cases and stimulus to improve functional coverage; Run regressions and drive verification closure; Collaborate with cross-geo teams to execute verification plans.
Seniority
Senior, hands-on IC