Senior Engineer - Memory Circuit Design Verification
Core
Verification of DRAM critical timings and full-chip analog/mixed-signal designs using SPICE-based simulation.
Role type
Senior IC verification engineer (analog/mixed-signal, memory)
Builds
Verification environments, testbenches, and sign-off analysis for DRAM and emerging memory products
Domain
Semiconductor, Memory (DRAM/HBM/SRAM), Analog/Mixed-Signal IC Design
Deliverable
production ML models
Required skills
SPICE simulation (FastSPICE/Primesim/FineSim/SpectreFx), DRAM critical timing verification, full-chip analog simulation, testbench development, functional coverage analysis, debugging pre-silicon designs
Preferred skills
Analog/mixed-signal circuit design, CMOS/FinFET technology knowledge, Static Timing Analysis (STA), SystemVerilog (SV), Universal Verification Methodology (UVM), Perl, Python, HBM/DRAM/SRAM experience
Technologies
Virtuoso, Hspice, Xcelium, SimVision, WaveView
Responsibilities
Perform SPICE-based verification for DRAM critical timings, conduct full-chip analog simulation across PVTs and speed grades, develop test cases and stimulus for functional coverage, build and maintain verification environments and testbenches, collaborate with global teams on verification flows
Seniority
Senior, hands-on IC