IO Design Architect – High Speed Memory Interfaces (m/f/d)
Core
Design new architecture, analysis, and validation of high-speed memory IO interfaces, combining hands-on circuit understanding with system-level thinking.
Role type
Senior IC IO Design Architect (High-Speed Memory)
Builds
Next-generation memory technologies (DRAM, NAND, NOR) and mixed-signal IO solutions
Domain
Semiconductor / High-Speed Memory Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed-signal IO block design, Schematic design, Circuit simulation (SPICE), Schematic entry (Cadence/Synopsys), Block-level behavior modeling, Unix/Linux environments
Preferred skills
Scripting (Python, TCL, SKILL, Perl), Extraction and modeling tools, Cross-functional design team collaboration
Technologies
Cadence, Synopsys, SPICE, Unix/Linux
Responsibilities
Define and own IO and PHY concepts for high-speed memory interfaces, Perform block-level simulation, analysis, and feasibility checks, Review and guide schematic-level implementation, Support verification, silicon bring-up, and debug activities, Collaborate with global cross-functional teams, Use automation and AI-based tools to improve modeling workflows
Seniority
Senior, hands-on IC