Principal Engineer-HIG HBM Architecture
Core
Design and develop next-generation High Bandwidth Memory (HBM) DRAM products and memory subsystem architectures for AI/ML solutions.
Role type
Principal Memory Subsystem Architect
Builds
Next-generation HBM memory subsystems and IP blocks for AI/ML applications
Domain
Semiconductor / Memory Technology / AI Infrastructure
Deliverable
production ML models
Required skills
Memory subsystem architecture, Memory controller design, PHY design, Signal integrity analysis, Network-on-Chip (NoC) architecture, Bus protocols (AXI, AMBA, AHB, DFI, HIF), Performance modeling, Gate count/power/area estimation, IP vendor engagement, RTL validation collaboration
Preferred skills
PhD in relevant field, EDA tools for design/verification, Multi-core systems, Coherent interconnects, PCIe/CXL protocols, Confidential compute, Virtualization, Security, Serial link protocols (UCIe)
Technologies
HBM, DDR, LPDDR, GDDR, AXI, AMBA, AHB, DFI, HIF, PCIe, CXL, UCIe, RTL, NoC
Responsibilities
Develop innovative memory subsystem architectures for HBM-based AI/ML solutions; Define Memory and RAS architecture requirements and drive end-to-end architectural specifications; Collaborate with internal and external partners to develop novel architectures and detailed IP requirements; Lead engagement with IP vendors for interface and functional IP blocks; Analyze benchmarks, workloads, and simulation results to identify performance and efficiency opportunities; Perform performance and performance/Watt modeling; Partner with RTL, validation, and multi-functional teams to ensure successful implementation; Drive microarchitecture definition and participate in performance simulation and benchmarking
Seniority
Principal, hands-on IC with strategic roadmap ownership