SR/STAFF ENGINEER, FECOS CPIE YE
Core
Lead strategic initiatives and yield improvement programs for DRAM/NAND/HBM technologies using data analytics and AI transformation.
Role type
Senior/Staff Process Integration Engineer (Yield Engineering)
Builds
Yield models, benchmarking methodologies, and standardized best practices for semiconductor fabrication.
Domain
Semiconductor manufacturing (DRAM/NAND/HBM)
Deliverable
production ML models | dashboards & analysis
Required skills
Yield analysis, statistical modeling, root-cause analysis, cross-functional project leadership, data analytics tools (Yield3, JMP, Python), process integration concepts
Preferred skills
Machine learning, fabrication process knowledge, backend and reliability implications, BKM deployment
Technologies
Yield3, JMP, Python
Responsibilities
Lead high-impact cross-functional initiatives to drive yield improvement; Develop and enhance yield models for DRAM/NAND/HBM technologies; Lead YE SWAT team to define and deploy best practices across global network; Perform root-cause analysis via Model-Based Problem Solving approach.
Seniority
Senior/Staff, hands-on IC with strategic leadership
