ADTT Dry Etch MTS/SMTS
Core
Lead the development, characterization, and optimization of Dry Etch processes for advanced DRAM structures.
Role type
Senior IC semiconductor process engineer (dry etch)
Builds
Advanced DRAM memory structures
Domain
Semiconductor manufacturing / Memory technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Dry Etch process development, Plasma etch mechanisms, Process control, Defect mitigation, Cross-functional team leadership, Root cause analysis, Technical roadmap definition, Equipment vendor interface
Preferred skills
High aspect ratio etching, Critical dimension control, Selectivity challenges, Data analytics, DOE methodologies, SPC tools, Sub-20nm integration challenges
Technologies
Lam, TEL, AMAT
Responsibilities
Lead development and optimization of Dry Etch processes for DRAM, Collaborate with integration and metrology teams, Define technical roadmaps for DRAM scaling, Evaluate new etch technologies and hardware, Mentor junior engineers, Interface with equipment vendors, Drive root cause analysis and continuous improvement, Present findings to executive leadership
Seniority
Senior, hands-on IC