Senior Silicon Validation Methodology Engineer - Low Power
Core
Own end-to-end low-power validation methodology from silicon to product for GPU, SoC, and CPU, defining test strategies, coverage bounds, and signoff criteria.
Role type
Senior IC silicon validation methodology engineer (low-power)
Builds
Reusable validation methodology, tools, metrics, and infrastructure for energy-efficient silicon products
Domain
Semiconductor / Low-power design and validation
Required skills
Low-power architecture and design expertise, silicon validation methodology, cross-functional consensus building, AI-enabled analysis, strategy setting under trade-offs, automation development
Preferred skills
Experience setting validation policy/playbooks, shipping methodology reuse across multiple chips/SKUs, expert debug of silicon low-power issues
Technologies
GPU, SoC, CPU, PVT, DVFS, clocking, power gating, idle power, SOL (speed of light)
Responsibilities
Define test scope, coverage bounds, and signoff criteria; Invent new validation approaches; Drive cross-functional consensus; Improve validation workflow with automation and AI; Translate architecture goals into multi-generation methodology
Seniority
Senior, hands-on IC with strategy & mentorship
