Senior Chip Design Engineer
Core
Design performance and power management related IPs for Networking silicon, collaborating with Architecture and Verification teams.
Role type
Senior IC chip design engineer (RTL)
Builds
Core IPs within Networking silicon
Domain
Semiconductor / Networking silicon
Deliverable
production ML models
Required skills
RTL Design, chip development, specification adherence, cross-team collaboration
Preferred skills
none stated
Technologies
none stated
Responsibilities
Design performance and power management related IPs; Develop core IPs within Networking silicon; Collaborate with Architecture, Micro-Architecture, verification, and Post-Silicon validation teams.
Seniority
Senior, hands-on IC
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