RTL Power Optimization Engineer – New College Grad 2026
Core
Develop AI-driven RTL and architecture power optimization solutions for next-gen GPUs and networking chips to improve energy efficiency.
Role type
Junior IC RTL Power Optimization Engineer
Builds
Pre-silicon power analysis tools, low-power design patterns, and power management improvements for NVIDIA GPUs and networking products.
Domain
Semiconductor / AI Hardware / Power Efficiency
Deliverable
production ML models | product features
Required skills
RTL power optimization fundamentals, Python programming, Machine Learning/AI application, backend flows (logic synthesis, place-and-route), low-power design techniques (clock gating, operand isolation, power gating), industry power analysis tools (PowerArtist, PrimeTime PX), RTL debugging
Preferred skills
MS/PhD in EE/CE, experience with AI/ML in EDA, Verilog prototyping
Technologies
Verilog, Python, PowerArtist, PrimeTime PX
Responsibilities
Use internal and industry tools for pre-silicon gate-level and RTL power analysis; develop and share best practices for power analysis; perform comparative power analysis to identify trends and anomalies; interact with architects and RTL designers to interpret power data and drive fixes; select and run workloads for power analysis; prototype new architectural features in Verilog and analyze power.
Seniority
Entry-level (New College Grad 2026)
