Principal Chip Lead, Silicon Co-Design Group
Core
Technical lead for high-consequence silicon programs, accountable for end-to-end technical integrity and guiding co-design feature integration across architecture, design, validation, and manufacturing.
Role type
Principal, strategy & mentorship (Silicon Co-Design Lead)
Builds
High-performance chips for Datacenter, Gaming, Robotics, Automotive, and Embedded markets
Domain
Semiconductor / SoC / ASIC
Deliverable
production ML models | product features | infrastructure
Required skills
SoC and ASIC architecture, post-silicon bring-up, validation, system integration, HBM, SerDes, power and thermal, packaging, multi-functional bug resolution, technical narrative shaping, cross-functional leadership without direct authority
Preferred skills
Chip Lead or Principal/Distinguished Engineer experience on flagship GPU/AI accelerator/CPU/networking ASIC, patent or conference paper history, reusable methodology development, AI tool usage for team velocity
Technologies
HBM, SerDes, high-speed I/O, packaging, SoC, ASIC
Responsibilities
Serve as single technical point of contact for multi-functional decisions; Co-lead program-level feature integration from chip to system; Resolve hardest multi-functional bugs; Steward the qualification playbook; Shape technical narrative for executive leadership; Mentor Chip Leads on adjacent programs; Lead Critical Debug and SCG Technical Execution forums
Seniority
Principal, strategy & mentorship
