Senior Lab DSP Communication Engineer
Core
Develop HW tools and flows to improve lab debuggability, correlate simulation results with lab measurements to improve model accuracy, and characterize analog/digital blocks for next-generation SerDes designs.
Role type
Senior IC signal processing and communications engineer (SerDes)
Builds
High-speed wireline communication links and SerDes architectures
Domain
Semiconductors / High-speed communications
Deliverable
production ML models | product features
Required skills
Signal processing, Communications, MATLAB development, High-speed communication systems, Mixed-signal processing, Analytical problem solving
Preferred skills
Signal integrity, Chip design, Mixed signal design, Python development, Hands-on lab experience in communication systems
Technologies
MATLAB, Python
Responsibilities
Develop HW tools and flows to improve lab debuggability and visibility; Correlate simulation results with lab measurements to improve model accuracy; Characterize and evaluate analog and digital blocks in the lab to contribute to DSP architecture and modeling strategies; Find performance bottlenecks; Work closely with cross-disciplinary teams to ensure accurate and reliable model representation.
Seniority
Senior, hands-on IC