Senior Power Analysis and Optimization Engineer
Core
Senior engineer combining power architecture expertise with machine learning, reinforcement learning, and LLMs to model, analyze, and optimize energy consumption across full-chip and unit-level GPU/SoC designs.
Role type
Senior IC power architecture & optimization engineer (AI/ML enabled)
Builds
Energy-efficient GPUs and Tegra SoCs
Domain
Semiconductor hardware design (ASIC/GPU) + AI/ML
Deliverable
production ML models
Required skills
Power architecture, energy consumption modeling, low-power design, Verilog, ASIC design principles, Python, Perl, C++, machine learning, reinforcement learning, LLMs/foundation models, data analytics, automation scripting
Preferred skills
Experience with EDA tools (PowerArtist, PrimePower, RTL Architect), building engineering copilots, cross-functional collaboration
Technologies
Python, Perl, C++, Verilog, PowerArtist, PrimePower, PrimePower RTL, RTL Architect, LLMs, Reinforcement Learning
Responsibilities
Analyze full-chip and unit-level power using RTL/gate-level tools; Develop and productionize power-aware ML/RL models for anomaly detection and dynamic power management; Design and train LLMs to interpret power data and recommend optimizations; Prototype architectural features in Verilog focusing on power implications; Automate power analysis flows and pipelines; Partner with architecture, performance, and design teams to drive power fixes.
Seniority
Senior, hands-on IC
