CareerPlanSign in

Senior Circuit Design Engineer - Noise

US, CA, Santa Clara💼 Full-time💰 $168,000–$168,000🗓 2026-07-24 → 2026-09-25

Core

Design innovative circuits (digital, semi-custom, mixed-signal analog) for silicon correlation and noise mitigation in deep submicron technologies.

Role type

Senior IC circuit design engineer (noise mitigation)

Builds

Next-generation NVIDIA processors and silicon products

Domain

Semiconductor / Deep submicron process / Analog & Mixed-Signal

Deliverable

production ML models | product features

Required skills

Deep submicron process knowledge, Analog/Mixed-Signal block design (op-amp, comparator, ADC), Spice simulation, EM/IR analysis, Static timing analysis/closure, Transistor-level analysis, Mentorship

Preferred skills

Voltage sensor design, Flash ADC design, RTL/Logic synthesis/verification, Place and Route, DFT, Scripting (Perl, Tcl, Make)

Technologies

Spice, EM/IR tools, Static timing analysis tools, Custom/automated design tools

Responsibilities

Design innovative circuits for silicon correlation and noise mitigation, Perform detailed transistor-level analysis to improve performance and reliability, Drive design and physical implementation of digital/mixed-signal circuit IPs, Create and deploy prototypes of patentable ideas on test chips, Mentor junior team members

Seniority

Senior, hands-on IC with mentorship

Sourced via workday · Listed on CareerPlan, which tracks 70,000+ jobs from 20+ sources.