Sr Engineer, TSE-DRAM
Core
Develop, debug, and maintain code for parallel testing of advanced DRAM memory devices, optimizing test flows and algorithms to reduce test times and manufacturing costs.
Role type
Senior IC semiconductor test engineer (DRAM)
Builds
Production test flows, test programs, and DFT/DFM/DFR capabilities for DRAM products
Domain
Semiconductor manufacturing / Memory testing
Required skills
C++ programming, Python/Perl scripting, Unix/Linux command line, Digital logic gates, CMOS transistor operation, DRAM memory device physics, Statistical Process Control (SPC), Data analysis, Semiconductor memory testers (ATE), Algorithm pattern generation (APG), CMOS manufacturing
Preferred skills
None stated
Technologies
C++, Python, Perl, Unix/Linux, ATE platforms
Responsibilities
Design test plans and algorithms for DRAM covering software/hardware requirements and defect coverage; Develop test programs for products using C++ and Python on Automated Test Equipment (ATE); Optimize test programs to reduce product test times and manufacturing costs; Independently debug and identify root causes of test issues; Provide statistical data analysis and justification for program validation; Evaluate and verify yields/quality with global teams; Lead teams in development of new processes and capabilities to support product roadmap.
Seniority
Senior, hands-on IC
