Staff Memory Design Engineer, HBM
Core
Designing, simulating, and optimizing DRAM circuits (digital, analog, and memory core) for advanced memory products, utilizing AI-enabled tools and leading layout development.
Role type
Staff IC memory design engineer (DRAM/HBM)
Builds
High-performance DRAM chips and memory subsystems for data centers and AI applications
Domain
Semiconductor / Memory / HBM
Deliverable
production ML models | product features
Required skills
CMOS circuit design, VLSI, analog circuit design, DRAM subsystem architecture, circuit floor planning, layout leadership, cross-functional technical leadership
Preferred skills
Problem-solving, industry technology trends knowledge, cross-functional collaboration
Technologies
Cadence Virtuoso, FINESIM, HSPICE, VERILOG
Responsibilities
Design digital, analog, and memory core circuits from concept to solution; create optimized floorplans for placement, routing, power delivery, and timing; conduct circuit simulations and analyze power/performance/reliability; validate builds via reticle experiments and tape-out revisions; manage layout resources and track project tasks; lead design reviews and prepare status reports
Seniority
Staff, hands-on IC with strategic influence