Semiconductor Principal Design Engineer
Core
Lead the design, layout, and optimization of datapath circuits and TSV interfaces for NAND flash memory products, ensuring timing closure and signal integrity across highly parallel architectures.
Role type
Principal Design Engineer (Memory Circuit Design)
Builds
NAND flash memory products with advanced 3D-stacked architectures (TSV, HBM-like)
Domain
Semiconductor / Memory / High-Speed Digital Design
Deliverable
production ML models | product features
Required skills
TSV interface circuit design, high-speed memory interface design (DDR4/5, LPDDR5/6, HBM3/3E/4), timing analysis, parasitic modeling, signal integrity, power integrity, CMOS device reliability, BSIM models, clock distribution, skew management, parallel bus optimization, DFT design, post-silicon debug
Preferred skills
AI integration in design workflows, chip-level PDN optimization, physical design
Technologies
Verilog, TSV, HBM, DDR, LPDDR, CMOS, BSIM
Responsibilities
Design and optimize TSV interface circuits including Rx/Tx circuits and impedance matching; Develop and characterize TSV electrical models; Define signal and power integrity requirements for TSV channels; Architect data paths from page buffers to TSV output interfaces; Develop clocking and synchronization strategies for parallel internal buses; Perform timing analysis across the datapath under PVT variations; Support post-silicon validation, debug, and tape-out revisions.
Seniority
Principal, hands-on IC with strategic decision-making