Semiconductor Principal Design Engineer
Core
Design and optimize datapath circuits for NAND flash memory, specifically focusing on TSV (Through-Silicon Via) interfaces, high-speed parallel buses, and signal/power integrity.
Role type
Principal Design Engineer (Memory Circuit Design)
Builds
NAND flash memory products with 3D-stacked architectures
Domain
Semiconductor / Memory / High-Speed Interface
Required skills
TSV interface circuit design, high-speed memory interface design (NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), timing analysis, parasitic modeling, signal integrity, power integrity, CMOS device modeling, parallel bus optimization, DFT design, clock distribution, tape-out management
Preferred skills
AI application in design workflow, chip-level PDN optimization, CMOS BSIM model expertise, physical design
Technologies
Verilog, TSV, HBM, DDR, LPDDR, NV-LPDDR4, CMOS, BSIM
Responsibilities
Design and verify TSV-specific DFT circuits, define signal and power integrity requirements, architect data paths from page buffer to TSV output, manage timing closure across parallel buses, collaborate with process technology and packaging teams, support post-silicon validation and debug, drive silicon experiments for yield improvement.
Seniority
Principal, hands-on IC with strategic decision-making
