Senior DRAM Security Test Engineer
Core
Develops advanced security validation infrastructure to assess the resilience and effectiveness of security mitigations in modern memory products.
Role type
Senior IC DRAM Security Test Engineer
Builds
Scalable FPGA-based platforms, software frameworks, and automation systems for DRAM validation and characterization
Domain
Semiconductor / Memory Systems / Hardware Security
Deliverable
production ML models | product features | infrastructure
Required skills
FPGA development (Verilog, SystemVerilog, VHDL), Python, C++, hardware/software integration, automation, debugging, memory systems knowledge, AI-assisted development tools
Preferred skills
DRAM architecture, JEDEC protocols, ATE, PCIe, AXI, DMA, high-performance data movement architectures
Technologies
Xilinx Vivado, Intel Quartus, Claude, LLMs
Responsibilities
Design and maintain security-focused DRAM test infrastructure; Develop FPGA-based platforms for complex command sequences; Build software frameworks and automation pipelines; Use AI tools for coding, RTL generation, and debugging; Create tools for prototyping and deployment of security validation methodologies; Integrate host software, FPGA, PCIe, and DRAM subsystems; Partner with security researchers and architects; Analyze validation campaign results; Drive platform scalability and automation improvements; Define roadmap for next-generation infrastructure
Seniority
Senior, hands-on IC
