Principal Design Engineer
Core
Design and verify major IO/datapath blocks (receivers, serializer, clock distribution, equalizers, ZQ calibration, ONFI training, wave pipelines) for high-speed memory and storage solutions, leveraging AI tools to accelerate exploration, sizing, and verification.
Role type
Principal IC design engineer (high-speed IO)
Builds
Memory and storage chips (DRAM, HBM, DDR interfaces)
Domain
Semiconductor / High-speed digital design
Deliverable
production ML models | product features
Required skills
High-speed IO design, physical design flows, layout optimization, parasitic extraction, CMOS device physics, BSIM modeling, AI tool usage (LLMs, agentic workflows), prompt engineering
Preferred skills
DRAM interface experience (DDR4/5, LPDDR5/6, HBM3/4), custom AI agent deployment, RAG, fine-tuning, quantified productivity impact of AI changes
Technologies
LLMs, code/RTL generation, spec parsing, waveform interpretation, layout engines, ML-based EDA, DDR4/5, LPDDR5/6, HBM3/4
Responsibilities
Design and verify major IO/datapath blocks to meet performance specs; Champion AI adoption by evaluating tools and publishing standard methodologies; Work with integration and Apps teams to define interfaces and evaluate new specifications; Document AI-augmented methodologies and mentor engineers on AI-first workflows
Seniority
Principal, hands-on IC design & AI strategy