APTD Process Integration Technician
Core
Execute wafer matching, lot pairing, and bonding operations while monitoring parametric indices and troubleshooting line deviations in semiconductor manufacturing.
Role type
Process Integration Technician (Wafer Matching & Bonding)
Builds
Semiconductor memory and storage products (DRAM, NAND, NOR)
Domain
Semiconductor Manufacturing / Wafer Processing
Deliverable
production ML models | product features | dashboards & analysis | infrastructure | physical/clinical work
Required skills
Wafer matching and lot pairing, Bonding UI configuration, Wafer shuffling, Inline inspection coordination, Data extraction and analysis from SWR/Conversion experiments, Wafer shipment logistics, Parametric index monitoring, Micron Central/DataNav/SPACE systems usage, SPC (Statistical Process Control), SWR (Statistical Wafer Review), QDR (Quality Data Review), Basic knowledge of fabrication processes (Photo, Dry Etch, Diffusion, CVD, Wet Etch, Plating, Implant, PVD, CMP)
Preferred skills
FE MES and LMS experience, Basic computer language scripting/AI skills
Technologies
Micron Central, DataNav, SPACE, SWR, Conversion experiments, Klarity
Responsibilities
Configure bonding UI and track development lots, Apply AI-enabled ways of working to improve efficiency, Assist PI Engineers to coordinate and troubleshoot daily line issues, Support process flow setup activities for production, Extract and summarize data from experiments for engineering recommendations, Manage wafer shipment logistics between fabs, Monitor key inline/probe/final parametric indices for deviations
Seniority
Individual Contributor, operational level