Principal Design Engineer
Core
Lead the development, layout, and optimization of datapath circuits for next-generation NAND flash memory, acting as a key technical leader driving architectural decisions and mentoring talent.
Role type
Principal Design Engineer (IC Physical Design)
Builds
Next-generation NAND flash memory chips
Domain
Semiconductor / Memory Technology
Deliverable
production ML models | product features | infrastructure
Required skills
High-speed IO circuit design, physical design flows, layout optimization, parasitic extraction, chip architecture/floorplanning, power/area optimization, silicon debugging, project management
Preferred skills
AI application in design workflow, DRAM interface experience (DDR4/5, LPDDR5/6, HBM3/3E/4), signal/power integrity (SI/PI), chip-level power delivery network (PDN) design, CMOS device physics and reliability modeling
Technologies
NAND flash, DDR4/5, LPDDR5/6, HBM3/3E/4, BSIM modeling, ONFI training, ZQ calibration
Responsibilities
Manage and verify major IO/datapath blocks to meet performance specifications; Model layout parasitics and optimize signal quality, area, and power; Collaborate with integration teams to define block interface specifications; Partner with Product Engineering to drive silicon experiments and debugging; Liaise with Applications Engineering to evaluate new specification feasibility; Mentor engineers and present technical results to expert panels
Seniority
Principal, hands-on IC design leader