Sr Design Engineer, DEG Design Method
Core
Design, optimize, and verify block-level circuits for DRAM projects, bringing innovative circuit designs from concept to silicon.
Role type
Senior IC design engineer (mixed-signal/analog/digital)
Builds
DRAM memory products and circuit designs
Domain
Semiconductor / Memory and Storage
Deliverable
production ML models | product features
Required skills
Mixed-signal, digital, or analog IC design; Regulator, charge pump, oscillator, current reference, bandgap, or comparator design; SPICE and Verilog modeling and simulation; Agentic and GenAI systems experience
Preferred skills
Mixed-signal or analog IC design experience; Circuit debugging with cross-functional teams; UNIX and Cadence design environment (schematic, simulation, SPF extraction); Synopsys tools
Technologies
SPICE, Verilog, Cadence, Synopsys, UNIX
Responsibilities
Design, optimize, and verify block-level circuits for DRAM projects; Compare silicon performance with simulation results and support correlation activities; Collaborate with process integration and modeling teams on new process node development; Partner with global design groups and provide layout guidance through post-layout simulation
Seniority
Senior, hands-on IC