Sr. Principal/SMTS, IO/Clock Design Engineering
Core
Architecting, designing, optimizing, verifying, and supporting high-speed IO and clocking circuits for DRAM memory products.
Role type
Sr. Principal/SMTS high-speed IO/Clock Design Engineer
Builds
Critical high-speed IP circuits for Micron's DRAM memory products
Domain
Semiconductor / Memory / High-speed digital design
Deliverable
production ML models | product features
Required skills
High-speed IO interface design, timing and clocking circuit design, equalization techniques, bandwidth extension, jitter and duty cycle distortion analysis, full-chip simulation, layout practices for high-speed circuits, mentoring engineers
Preferred skills
DRAM circuit design, channel modeling, transceiver noise analysis, timing budget analysis, SI knowledge, device physics, CMOS processing, scripting (Perl/Python), AI/ML usage
Technologies
Perl, Python, Agentic AI
Responsibilities
Define, innovate, design, optimize and verify high-speed IO and clocking circuits; Apply robust high-speed circuit design techniques to enhance performance evaluation of IO and clock paths; Develop accurate modeling, analysis and simulation methodology; Work with Product Engineering and SI team to compare silicon performance with simulation results; Collaborate with process integration and transistor modeling teams on next process node
Seniority
Sr. Principal/SMTS, hands-on IC with mentorship