Photomask R&D Process Integration Engineer
Core
Integrating photomask technologies to enable manufacturability for next-generation memory products, specifically High NA EUV.
Role type
Senior IC process integration engineer (photomask R&D)
Builds
Next-generation memory scaling solutions (High NA EUV photomasks)
Domain
Semiconductor manufacturing / Photomask technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor process integration, Design of Experiments (DOE), statistical data analysis, project leadership, cross-functional collaboration
Preferred skills
Photomask process development, Model-Based Problem Solving, yield improvement strategies, external partner collaboration
Technologies
High NA EUV, DRAM, NAND
Responsibilities
Lead integration efforts for next-generation photomask manufacturability; Design and implement experiments in mask and wafer fabs; Optimize process flows to meet performance, yield, and cost targets; Drive yield improvement initiatives; Partner with mask R&D, design, and photolithography teams
Seniority
Senior, hands-on IC