CareerPlan

Process Engineer 5

US-CA-Fremont (1003)Full-time2026-10-28 → 2026-11-10

Core

Develop and optimize plasma etch processes for advanced semiconductor patterning schemes, including EUV and multi-patterning, to support next-generation chip manufacturing.

Role type

Senior IC process engineer (plasma etch)

Builds

Advanced etch equipment and systems for semiconductor customers

Domain

Semiconductor manufacturing / Plasma physics

Required skills

Plasma etch process development, Reactive Ion Etching (RIE), EUV patterning, multi-patterning (SADP/SAQP), CD control, metrology analysis (CD-SEM, TEM), statistical process control (SPC), Design of Experiments (DOE), MATLAB/Python, cross-functional collaboration, technical leadership

Preferred skills

Atomic Layer Etching (ALE), ICP/CCP systems, high-aspect-ratio etch, failure analysis, deposition process integration (ALD/CVD/PVD), JMP/Minitab

Technologies

CD-SEM, TEM, AFM, JMP, Minitab, MATLAB, Python, ICP, CCP, EUV, SADP, SAQP

Responsibilities

Conduct plasma etch R&D and evaluation; develop/optimize etch processes for advanced patterning; characterize etch performance (profile, CD, LER/LWR); analyze metrology data; collaborate with lithography/deposition teams and customers; drive adoption of new technologies; provide leadership to process technicians.

Seniority

Senior, hands-on IC