SoC Architect - Low Power Design ( HBM)
Core
Define, model, and drive SoC-level power architecture for next-generation HBM logic die and memory-centric SoCs to deliver industry-leading performance-per-watt solutions.
Role type
Senior IC SoC Architect (Low Power Design)
Builds
Next-generation HBM logic die and memory-centric SoCs
Domain
Semiconductor / Memory / High-Performance Computing
Deliverable
production ML models
Required skills
SoC/system-level architecture, low-power design techniques (DVFS, power gating, clock gating), power modeling and analysis, RTL design concepts, UPF/CPF flows, RTL-to-GDS flow knowledge, cross-functional technical leadership, Python/C/C++/TCL scripting
Preferred skills
HBM/DRAM/memory-centric SoC experience, GPU/CPU/high-performance accelerator architecture background, industry power standards familiarity (ARM, SCMI), silicon power measurement and post-silicon debug, emulation/prototyping platform experience, Master's or PhD in EE/CE, 10+ years of relevant industry experience, Agentic AI workflow knowledge
Technologies
SystemVerilog, UPF, CPF, Python, C, C++, TCL
Responsibilities
Define and own SoC-level low-power architecture including power domains, voltage islands, clocking strategies, and low-power operating modes; Develop power, performance, and thermal models to evaluate architectural tradeoffs; Architect and drive implementation of power management features such as DVFS, clock gating, power gating, and adaptive performance controls; Collaborate with SoC and subsystem architects to translate product requirements into power-aware micro-architectural specifications; Partner with RTL, verification, and physical design teams to ensure correct implementation of power intent and debug power-related issues; Work with firmware and software teams to define hardware-software power management interfaces and control flows; Drive performance vs. power analysis to support product decisions and roadmap planning; Support pre-silicon validation and post-silicon bring-up including silicon power characterization and root-cause analysis; Mentor junior architects and engineers in low-power design best practices
Seniority
Senior, hands-on IC with mentorship
