Product Failure Analysis Engineer - SCAN Design for Test
Core
Lead root-cause analysis of silicon failures in advanced process technologies (18A) using logical and physical failure analysis methods to improve product quality and yield.
Role type
Senior IC Product Failure Analysis Engineer (Silicon Debug & DFT)
Builds
Intel Foundry 18A technology products for next-generation foundry customers
Domain
Semiconductor manufacturing / Advanced node silicon debug
Required skills
DFT architecture design, ATPG pattern generation, scan chain diagnosis, fault modeling (stuck-at, transition, path delay, bridging), physical failure analysis (FIB, SEM, TEM), debug automation scripting (Python, Perl, TCL), cross-functional technical leadership
Preferred skills
JTAG validation research, innovative debug tool development, foundry/fabless HVM environment experience
Technologies
Siemens Tessent, Synopsys TestMAX/TetraMAX, Verdi, DVE, FIB tools, probe tools
Responsibilities
Isolate microscopic silicon circuit failures using state-of-the-art lab equipment; Partner with design, test, and manufacturing teams to resolve quality issues; Develop new debug tools and methodologies to accelerate root-cause identification; Evaluate design-for-debug features; Provide expert input on failure analysis investigation areas
Seniority
Senior, hands-on IC
