GPU IP Integration Model Build Engineer
Core
Functional verification model integration of graphics logic components (3D graphics, media) to ensure design meets specification requirements.
Role type
Senior IC verification model build engineer (GPU IP)
Builds
Graphics and media IP components for SoC integration
Domain
Semiconductor / VLSI / Graphics IP
Deliverable
production ML models | product features
Required skills
pre-silicon simulation model builds, VLSI design, test environment architecture, Verdi, VCS, UVM/OVM, digital logic design (FSM, registers, counters), IP validation flows, Python/Perl/Ruby scripting, problem diagnosis
Preferred skills
media industry trends and technologies
Technologies
Verdi, VCS, UVM, OVM, Python, Perl, Ruby
Responsibilities
Integrate functional verification models for graphics and media logic; define verification infrastructure and TFMs; architect and implement IP test environments (checkers, monitors, VC); collaborate with cluster owners to integrate code into media IP; diagnose problems and implement sustainable solutions
Seniority
Senior, hands-on IC
