Senior Design Verification Engineer - Neuromorphic Computing
Core
Develop and scale pre-silicon verification methodologies for neuromorphic computing architectures, spanning software APIs, RTL, and emulation platforms to validate event-driven, sparse, and massively parallel neuro-inspired processing.
Role type
Senior IC pre-silicon verification engineer (neuromorphic/ASIC)
Builds
Neuromorphic research chips (Loihi series) and physical AI systems
Domain
Semiconductor / Neuromorphic Computing / AI Hardware
Deliverable
production ML models
Required skills
UVM, constrained random verification, Python test generation, HDL-based verification environment development, coverage tracking, assertion/scoreboard maintenance, VIP integration, emulation, post-silicon validation
Preferred skills
Neuromorphic computing, AI/ML accelerator design, commercial Verification IPs (Ethernet, PCIe, MACsec/IPsec, RoCEv2, MIPI CSI-2, JESD204), DFX, low power, UPF verification
Technologies
Python, UVM, HDL, emulation platforms, AI tools for test generation
Responsibilities
Map application-level requirements to unit- and system-level test plans; Write Python-based directed and random tests for design partitions and chip-level; Run regressions, debug test failures, track coverage, and collaborate with designers to fix failures; Maintain assertions, scoreboards, and verification tools/flows; Integrate VIPs and coordinate with IP teams to ensure protocol requirements are met
Seniority
Senior, hands-on IC
