MTS Analog I/O Design Engineering
Core
End-to-End development of IO IPs including GPIO, LVDS, SSTL, HSTL, and MIPI across multiple technology nodes.
Role type
Senior IC analog I/O design engineer
Builds
IO IP blocks for semiconductor foundry customers
Domain
Semiconductor manufacturing / Analog I/O design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CMOS design, Analog and I/O IP development, Circuit design, Simulation verification, Reliability assurance, Test chip design, Packaging design, Post-silicon testing, Layout supervision, Market competition analysis
Preferred skills
High Speed I/O Design, Low-power design techniques, IO reliability, RTL design (Verilog/VHDL), Synthesis, Timing closure, ESD design, Pad ring design, Physical verification flows, Silicon validation, Lab debug tools
Technologies
GPIO, LVDS, SSTL, HSTL, MIPI, Verilog, VHDL
Responsibilities
Develop and deliver IO IPs achieving PPA indicators, Define IO IP architecture and circuit design, Collaborate on test chip and packaging design, Supervise layout engineers, Participate in market competition analysis
Seniority
Senior, hands-on IC
