Senior ASIC Design Engineer
Core
Design digital logic modules for next-generation firewall platforms, owning the flow from specification through silicon bring-up.
Role type
Senior ASIC Design Engineer
Builds
Digital logic modules for high-performance network security hardware
Domain
Cybersecurity hardware / ASIC design
Required skills
SystemVerilog RTL, micro-architecture definition, datapath design, timing/power/area analysis, complex IP integration, scripting (Python/C++/Perl/bash)
Preferred skills
Networking/cybersecurity domain knowledge, search-algorithm accelerator experience, formal verification ownership, silicon validation
Technologies
SystemVerilog, Python, C++, Perl, bash, tcsh, PCIe, Ethernet, DDR
Responsibilities
Write design and micro-architecture specifications; Design RTL meeting area/performance/power targets; Verify blocks via simulation/emulation/formal methods/silicon bring-up; Collaborate on debugging and coverage closure; Partner with physical-design teams on timing reports and floor-planning; Pilot AI-driven design flows
Seniority
Senior, hands-on IC
