IP-Post Silicon Validation Engineer
Core
Planning, validation, and debugging of hardware IP for AMD APU, CPU, Compute, and Discrete Graphics SOC programs.
Role type
Senior IC IP Validation Design Engineer
Builds
AMD APU, CPU, Compute, and Discrete Graphics SOC programs
Domain
Semiconductor / Processor Architecture
Required skills
SoC architecture, ASIC debug techniques, digital logic design/verification, scripting (Ruby, Python), protocol/logic analyzer usage, board/platform-level debug
Preferred skills
High-speed interface knowledge, IOMMU IP architecture, clock/power delivery analysis, leadership and mentoring
Technologies
Ruby, Python, Logic Analyzers, Oscilloscopes
Responsibilities
Define and execute functional test plans and validation strategies, debug IP issues across pre-silicon to production phases, collaborate with architects on technical solutions, develop validation tools and automation scripts, engage in pre-silicon shift-left activities with DV and emulation teams.
Seniority
Senior, hands-on IC
