CareerPlan

Technical Program Manager-Post Silicon Development

San Jose, CaliforniaFull-time2026-10-16 → 2026-10-22
On-siteNo visa sponsorship

Core

Manage a Silicon Engineering group and lead the FPGA-based ASIC design cycle, validation, and software integration to deliver next-generation computing technologies.

Role type

Senior Technical Program Manager (Silicon Development)

Builds

Next-generation ASICs and computing technologies

Domain

Semiconductor / Hardware Engineering

Required skills

FPGA-based ASIC design cycle knowledge, Vivado flows, project management, cross-functional team leadership, risk mitigation, stakeholder alignment, process improvement

Preferred skills

Managing complex interrelated ASIC projects, leading medium-to-large tech programs, liaising between IP/Validation/Software/SOC teams, proficiency with Jira/Confluence

Technologies

FPGA, ASIC, Vivado, Jira, Confluence, Microsoft Office Suite

Responsibilities

Manage and handle issues and escalations with a sense of urgency, Identify action or mitigation plans for issues or risks that arise during the project lifecycle, Facilitate closure of complex issues requiring multi-party alignment of AMD teams, customers, and partners, Initiates significant changes to existing processes and methods to improve project and team efficiency, Provides unique views and facilitates cross development team dependencies and communications, Has responsibility for projects or processes of significant technical importance and for results that cross engineering project areas

Seniority

Senior, hands-on IC