IP Post-Silicon Validation Lead
Core
Lead post-silicon validation, debugging, and test planning for AMD hardware IP (NBIO) within APU, CPU, and GPU SoC programs.
Role type
Senior IC IP Validation Design Lead
Builds
AMD APU, CPU, Compute, and Discrete Graphics SoCs
Domain
Semiconductor, SoC Architecture, Hardware Validation
Required skills
SoC architecture, ASIC debug, digital logic verification, post-silicon validation, functional test planning, cross-functional collaboration, scripting (Ruby/Python), lab equipment usage (logic analyzers, oscilloscopes)
Preferred skills
High-speed interface protocols, board/platform-level debug, PCIe architecture knowledge, leadership and mentoring
Technologies
Ruby, Python, Logic Analyzers, Oscilloscopes, PCIe
Responsibilities
Define and execute functional test plans and validation strategies; debug IP issues across pre-silicon, bring-up, and production phases; collaborate with architects to resolve technical risks; drive technical innovation in validation tools and methodologies; support customer platform issues.
Seniority
Senior, hands-on IC with mentoring responsibilities
