Next Gen CPU Power Management RTL Design Engineer
Core
Define and develop microarchitecture solutions for processor clocking, reset, and power management IP used in next-generation AMD CPUs.
Role type
Senior IC CPU Power Management and Clocking Micro-architect
Builds
Next-generation Ryzen, Threadripper, and EPYC processors
Domain
Semiconductor / CPU Design
Required skills
Verilog/SystemVerilog, C/C++ firmware, microarchitecture definition, RTL development, clock domain crossing, power gating, DVFS, silicon validation
Preferred skills
Low-power design strategies, thermal management, design-for-test methodologies, hardware-software interaction
Technologies
Verilog, SystemVerilog, C, C++, RTL, SoC
Responsibilities
Define microarchitecture solutions for clocking, reset, and power management IP; Collaborate with cross-functional teams to integrate power management features; Author microarchitecture specifications and technical documentation; Develop high-quality RTL and contribute to firmware development; Drive design quality through lint, CDC analysis, and debugging; Support silicon validation, debug, and product bring-up activities
